HCPL 4661 PDF

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High Speed: 10 MBd Typical? Low Input Current Capability: 5 mA? Isolated Line Receiver? Computer-Peripheral Interfaces? Microprocessor System Interfaces? Switching Power Supply? Ground Loop Elimination? Pulse Transformer Replacement? Power Transistor Isolation in Motor Drives? An enable input allows the detector to be strobed. F bypass capacitor must be connected between pins 5 and 8.

This unique design provides maximum ac and dc circuit isolation while achieving TTL compatibility. Technical data are on separate HP publications. Contact Hewlett-Packard sales representative or authorized distributor for information. Combination of Option and Option is not available. Gull wing surface mount option applies to through hole parts only.

Measured from input terminals to output terminals, shortest distance path along body. Through insulation distance, conductor to conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity.

Measured from input terminals to output terminals, along internal cavity. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. High Level Enable Voltage? It is recommended that 6. For single channel products only.

All enable test conditions apply to single channel products only. See note 5. Note 20, 21 20, 21 20, 22 1, 20, 23 1, 20, 23 24 RI-O? Notes: 1. Each channel. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 20 mA. Peaking circuits may produce transient input currents up to 50 mA, 50 ns maximum pulse width, provided average current does not exceed 15 mA. Bypassing of the power supply line is required, with a 0.

F ceramic disc capacitor adjacent to each optocoupler as illustrated in Figure Total lead length between both ends of the capacitor and the isolator pins should not exceed 20 mm. HP guarantees a maximum IOH of ? HP guarantees a maximum IEL of The tPLH propagation delay is measured from the 3. The tPHL propagation delay is measured from the 3. The tELH enable propagation delay is measured from the 1. The tEHL enable propagation delay is measured from the 1.

CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state i. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state i. No external pull up is required for a high logic state on the enable input. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together, and pins 5, 6, 7, and 8 shorted together.

Measured between the LED anode and cathode shorted together and pins 5 through 8 shorted together. For dual channel products only. Measured between pins 1 and 2 shorted together, and pins 3 and 4 shorted together. Typical High Level Output Current vs.

Figure 2. Typical Output Voltage vs. Forward Input Current. Typical Input Threshold Current vs. Typical Low Level Output Voltage vs. Figure 5. Typical Low Level Output Current vs. Typical Input Diode Forward Characteristic. Typical Temperature Coefficient of Forward Voltage vs. Input Current. Typical Propagation Delay vs. Figure Pulse Input Current.

Typical Pulse Width Distortion vs. Typical Rise and Fall Time vs. Typical Enable Propagation Delay vs. Recommended Printed Circuit Board Layout.

The propagation delay from low to high tPLH is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. Similarly, the propagation delay from high to low tPHL is the amount of time required for the input signal to propagate to the output causing the output to change from high to low see Figure 8. PWD can be expressed in percent by dividing the PWD in ns by the minimum pulse width in ns being transmitted.

Propagation delay skew, tPSK, is an important parameter to consider in parallel data applica- tions where synchronization of signals on parallel data lines is a concern. If the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause the data to arrive at the outputs of the optocouplers at different times. If this difference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers.

Propagation delay skew is defined as the difference between the minimum and maximum propagation delays, either tPLH or tPHL, for any given group of optocouplers which are operating under the same conditions i. As mentioned earlier, tPSK can determine the maximum parallel data transmission rate. Figure 20 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers.

The figure shows data and clock signals at the inputs and outputs of the optocouplers. To obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. Propagation delay skew represents the uncertainty of where an edge might be after being sent through an optocoupler. Figure 20 shows that there will be uncertainty in both the data and the clock lines. It is important that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived.

From these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice tPSK. A cautious design should use a slightly longer pulse width to ensure that any additional uncertainty in the rest of the circuit does not cause a problem.

The tPSK specified optocouplers offer the advantages of guaranteed specifications for propagation delays, pulsewidth distortion and propagation delay skew over the recommended temperature, input current, and power supply ranges. Parallel Data Transmission Example.

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HCPL 4661 PDF

High Speed: 10 MBd Typical? Low Input Current Capability: 5 mA? Isolated Line Receiver? Computer-Peripheral Interfaces?

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